Title: ASICS Engineering Duration: Sep 7, 2026 - Mar 5, 2027 Hours Per Week: 37.00 Location: Farnborough TECHNICAL SKILLS: Must Have: 5+ year of RFIC work experience AMS simulations Experience of verification simulations of complete transceiver chains RF -andgt; Analogue Verilog-A Verilog-AMS Nice To Have: Digital verification skills The senior engineer will take on the verification of full Rx and Tx chains of an on-going design. They will help setup and debug simulation testbenches, report compliance to spec and validate device register controls for test. The tasks will include: Review of block specifications. Simulation and reporting compliance to specifications. Root cause any specification failures. Liaising with the chip lead to integrate the designs. Presentation of design for block-level reviews. ..... full job details .....